Conventionally, an IDDQ (IDD Quiescent) test, a variety of IDDQ tests, has been practically used as a testing method which can easily enhance quality of a test in a semiconductor integrated circuit (hereinafter, referred to as “LSI”) using a complementary metal-oxide semiconductor (hereinafter, referred to as “CMOS”) circuit. In the CMOS circuit in a state in which an external input is decided and an operation is stable, a DC (Direct Current) path is not present. For this reason, only a very minute off-leakage current flows to the CMOS circuit. If a defect causing a current abnormality is present in the LSI using the CMOS circuit, accordingly, the defect can easily be detected. An IDDQ test utilizes the feature.
In a stuck-at fault model to be the easiest fault model, a signal of a defective portion in the LSI is fixed to 1 or 0. In case of the stuck-at fault, when a basic cell for driving a wiring in a defective portion outputs a signal of a reversed logical value to a logical value fixed by a fault to the wiring in the defective portion, an abnormal current flows to the LSI. In a short-circuit fault between wirings which are adjacent to each other (which will be hereinafter referred to as a “bridge fault”), in the case in which a signal of one of the wirings which is short-circuited is driven to “0” and a signal of the other wiring is driven to “1”, the abnormal current flows to the LSI.
Recently, some defective portion isolating methods using an IDDQ test have been proposed by setting the stuck-at fault and the bridge fault as targets. A basic defective portion isolating method is as follows. First of all an IDDQ fault simulation (a simulation for obtaining a logical value of a portion corresponding to each fault to decide a detection or no-detection of the fault) is carried out by using logical connection information or adjacent wiring (signal) information of an LSI to be a testing target (hereinafter, referred to as a “target LSI”) to obtain detection/no-detection information about the assumed faults on each measuring point of an IDDQ test. The detection/no-detection information is caused to correspond to a result of the IDDQ test of the target LSI, thereby limiting fault candidates of the target LSI sequentially. The “detection/no-detection information” is, hereinafter, information about faults of the LSI which are detected on each measuring point and information about faults of the LSI which are not detected. The “measuring point” implies a time that inputs of the target LSI are set to measure an IDDQ value in the XDDQ test. In general, a plurality of measuring points is set in the IDDQ test.
In the case in which the test result is “pass” on a certain measuring point (the IDDQ value is equal to or smaller than a value decided to be a normal product), a fault candidate is a fault other than that detected on the same measuring point. On the other hand, in the case in which the test result on the certain measuring point is “fail” (the TDDQ value exceeds the value decided to be the normal product), the fault candidate is limited to a fault detected on the same measuring point (the fault candidate is limited to “a set of faults” in consideration of a plurality of faults). By carrying out the above procedure for a plurality of measuring points, the fault candidates are limited and the defective portion is isolated.
In a large scale logic LSI with several million logical gates or more, for example, a large number of faults (fault candidates) are assumed. For this reason, there is a problem in that an enormously long time is required for carrying out a calculation to limit the fault candidates by the above procedure and an excellent limitation to a sufficiently small number of fault candidates cannot be carried out. In order to solve the problem, there has been proposed a method of carrying out a limitation for a stuck-at fault and a bridge fault and solving simultaneous linear equations with a measured value of a IDDQ test set to be an unknown quantity, thereby specifying a plurality of faults (for example, see JP-A-10-19986) By a recent process microfabrication, however, the IDDQ value of the LSI has reached several mA or several hundreds mA in an extreme case, though the IDDQ was equal to or smaller than several μA to approximately 10 μA in an LSI manufactured in a conventional and not fine process. Furthermore, the IDDQ value has a great variation every measuring point, and an accurate judgement as to “pass” and “fail” is hard to perform in the method proposed in JP-A-10-19986, where only one specification value is assigned to each abnormal IDDQ value decided to be defective in the IDDQ test. For this reason, it is difficult to obtain a correct answer in case of the bridge fault in which a plurality of abnormal IDDQ values are present depending on an input state, for example. In the proposed method, therefore, it is hard to limit a defective portion with high precision.
Moreover, the IDDQ value has a characteristic as to be decreased considerably (to be equal to or greater than approximately one digit) by a reduction in a temperature, that is, a reduction to −40 degree from a room temperature, for example. Therefore, it is possible to propose a method of isolating a defective portion based on a result of a measurement at a low temperature. However, some IDDQ abnormalities are not observed at a low temperature even if they are observed at the room temperature, for example. For this reason, the method is not a perfect solution.